The Junction Field Effect Transistors (JFET)

The bipolar transistor has several disadvantages: it has low input impedance because of forward biased emitter junction, it has small high-frequency gain, it has considerable noise level and it is non-linear when |V_CE| < 2V. Although low input impedance problem may be improved by careful design and use or more than one transistor, even so it is difficult to achieve input impedance more than a few megaohms. The field effect transistor (FET) has, by virtue of its construction and biasing, has large input impedance which may be more than 100 megaohms. The FET is generally much less noisy than the bipolar transistor.

A junction field effect transistor is a three terminal semiconductor device in which current conduction is by one type of carrier i.e. electrons or holes. The current conduction is controlled by means of an electric field between the gate electrode and the conduction channel of the device. The JFET has high input impedance and low noise level.

The JFETs come in two types: n-channel and p-channel as shown in figure 1 below:

Construction Details of a JFET

A JFET consists of a p-type or n-type silicon bar contain two pn junctions at the sides as shown in figure 2 and figure 3 below. The bar forms the conduction channel for the charge carriers. If the bar is of n-type, it is called n-channel JFET and if the bar is of p-type, it is called a p-channel JFET. The two pn junctions forming diodes are connected internally and a common terminal called gate is taken out. Other terminals are source and drain taken out from the bar as shown in the figures below. Hence a JFET has essentially three terminals gate (G), source (S) and drain (D).

Principles of Operation of JFET

Let’s consider a circuit of n-channel JFT with normal polarities shown below. Note the gate is reverse biased.

The two pn junctions at the sides form two depletion layers. The current conduction by charger carriers (i.e. free electrons in this case) is through the channel between the two depletion layers and out of the drain. The width and hence resistance of this channel can be controlled by changing the input voltage V_GS. The greater the reverse voltage V_GS, the greater will be the depletion layers and narrower will be the conducting channel. The narrower channel means greater resistance and hence source to drain current decreases. The reverse will happen should V_GS decrease. Therefore JFET operates on the principle that width and hence resistance of the conducting channel can be varied by changing the reverse voltage V_GS. That is to say, the magnitude of drain current I_D can be changed by altering V_GS.

When a voltage V_DS is applied between drain and source terminals and voltage on the gate is zero, the two pn junctions at the sides of the bar establish depletion layers. The electrons will flow from source to drain through a channel between the depletion layers. The size of these layers determines the width of the channel and hence the current conduction through the bar.

When reverse voltage V_GS is applied between the gate and source, the width of the depletion layers is increased. This reduces the width of conducting channel, thereby increasing the resistance of n-type bar. Consequently, the current from source to drain is decreased. Alternatively, if the reverse voltage on the gate is decreased, the width of the depletion layers also decreases. This increases the width of the conduction channel and hence the drain current.

From the above discussion, the current from source to drain can be controlled by the application of potential (i.e. electric field) on the gate. For this reason, the device is called field effect transistor. Note that, a p-channel JFET operates in the same manner as n-channel JFET except that channel current carriers will be holes instead of electrons and the polarities of V_GS and V_DS are reversed. Another key point to note is that, if the reverse voltage V_GS is continuously increased, a state is reached when the two depletion layers touch each other and the channel is cut off. Under such conditions, the channel becomes a non-conductor.

Related: Bipolar Junction Transistors (BJT)

The characteristics curves of a typical JFET are shown in the figure below:

At small values of V_DS (in the range of a few tenths of a volt), the curves of constant V_GS shows a linear relationship between V_DS and I_D. This is the variable-resistance region of the graph. As V_DS increases, each of the curves of constant V_GS enters a region of nearly constant I_D. This is the pinch-off region, where the JFET can be used as a linear voltage and current amplifier. At V_GS = 0 the current through the JFET reaches a maximum known as I_DSS, the current from Drain to Source with gate Shorted to the source. If V_GS goes positive for this n-channel JFET, the PN junction becomes conducting and the JFET becomes just a forward-biased diode.